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SMB119 ? summit microelectronics, inc. 2006 757 north mary avenue ? sunnyvale ca 94085 ? phone 408 523-1000 ? fax 408 523-1266 1 http://www.summitmicro.com/ 2126 3.0 10/8/2008 seven-channel programmable dc-dc power manager introduction ? digital programming of all major parameters via i 2 c interface and non-volatile memory o output voltage setpoint/margining o sequencing & digital soft start o enable/disable outputs independently o input/output uv/ov voltage thresholds o pwm/pfm mode ? seven programmable regulator channels with 1.5% accuracy o three synchronous step-down (buck) with internal pfets o two step-up (boost) o one configurable step-up (boost) or step-down (buck) o one adjustable output voltage ldo ? +2.7v to +6.0v input range (higher system voltages supported) ? built-in current limiting, uv/ov, and thermal protection ? highly accurate reference and output voltage (<1.5%) ? 1mhz pwm frequency and automatic power-saving pfm mode ? 96 bytes of user configurable nonvolatile memory ? space-saving 7x7 qfn-48 package applications ? portable media players ? digital camcorders/still cameras ? smart pda/camera phones ? handheld gps/pdas ? portable equipment the SMB119 is a highly integrated and flexible seven-channel power manager designed for use in a wide range of portable applications. the built-in digital programmability a llows system designers to custom tailor the device to suit almost any multi-channel power supply application from digital camcorders to mobile phones. the SMB119 integrates all the ess ential blocks required to implement a complete seven-channel power subsystem including three synchronous step-down ?buck? c onverters, one configurable step-up ?boost? or step-down synchronous ?buck? converter, two step-up (boost) converters, and one linear regulator (ldo). additionally sophisticated power c ontrol/monitoring functions required by complex systems are built-in. these include digitally programmable output voltage setpoint, power-up/down sequencing, enable/disable, margining, dynamic voltage management, and uv/ov input/output monitoring on all channels. by incorporating a second enable input and 7-level dynamic voltage control, the SMB119 is ideal for powering systems based on xscale? and other similar processors. the integration of features and built-in flexibility of the SMB119 allows the system designer to create a ?platform solution? that can be easily modified via software without major hardware changes. combined with the re-programmability of the SMB119, this facilitates rapid design cycles and proliferation from a base design to futures generations of product. the SMB119 is suited to battery-powered applications with an input range of +2.7v to +6.0v and provides a very accurate voltage regulation (<1.5%). communicati on is accomplished via the industry standard i 2 c bus. all user-programmed settings are stored in non- volatile eeprom of which 96 bytes may be used for general-purpose memory applications. the commercial operating temperature range is 0c to +70c, the industrial operating range is ?40c to +85c, and the available package is a 48-pad 7mm x 7mm qfn. figure 1 ? applications block diagram featuring the SMB119 seven-channel, programmable dc/dc converter. this integrated power supply provides precision regulation, monitoring, cascade sequencing, and dynamic output voltage management. simplified applications drawing features & applications SMB119 +0.5v to vin (prog.) analog/rf +1.5v to +3.75v mcu/rtc ldo 3 step- down channels system control and monitoring status outputs shutdown +0.5v to +35v (prog.) memory, i/o +0.5v to vin (prog.) cpu core +0.5v to vin (prog.) dsp/codec step-up or step-down channel +2.7v to +6.0v dc in control inputs pushbutton power 2 step-up channels vin to +35v (prog.) led backlight vin to +35v (prog.) tft-lcd bias i 2 c/smbus system enable
SMB119 summit microelectronics, inc 3.0 10/8/2008 2 the SMB119 is a fully-programmable power supply that regulates, sequences, monitors, and margins, an entire power subsystem. the device has 7 voltage outputs, consisting of: three synchr onous pwm ?buck? step-down converters, one configurable pwm ?boost or buck? converter, two ?boost? step -up converters, and one low dropout (ldo) linear regulator. the SMB119 regulates each of the seven output channels to an accuracy of +/-1.5% (typical). the output is individually programmed and can be reprogrammed via the i 2 c interface. in addition, several sophisticated power management functions ar e built-in. the SMB119 is capable of power-on/of f cascade sequencing where each channel can be assigned one of eight sequence positions. supplies may also be individually powered on/off through an i 2 c command or by assertion of two general purpose enable pins. cascade sequencing, unlike time based sequencing, uses feedback to ensure that each output is valid before the next channel is enabled. each output voltage and the battery are monitored for under-voltage and over-voltage conditions, using a comparator based scheme. in the event of a fault, all supplies may be sequenced down or immediately disabled. multiple output stat us pins are provided to notify host processors or other supervisory circuits of system faults. the SMB119 features an under -voltage lockout (uvlo) circuit to ensure the ic will not power up until the battery voltage has reached a safe operating voltage. the uvlo function exhibits hysteresis, ensuring that noise on the supply rail does not inadvertently cause faults on the internally regulated supply. in the event of a system fault, all monitored supplies may trigger fault actions such as power-off, or force-shutdown operations. each output on the SMB119 may also be turned off individually at any point through an i 2 c command or by a programmable enable pin. when used in portable applications, the SMB119 is powered from the main system battery. this input is continuously monitored for under-voltage conditions. the under-voltage setting for this supply is user- programmable and has a corresponding status pin. when the threshold level is reached, the power_fail pin is asserted and latched. a second threshold level also exists that asserts a status bit flag. the SMB119 is equipped with three synchronous buck outputs and one ?buck-or-boo st? output that use a 1000khz oscillator frequency. the feedback circuitry on each step-down channel is simplified by an internal programmable resistor divider (buck-or-boost uses external resistor divider). the SMB119 is also equipped with two boost outputs. each boost output uses a 1000khz oscillator, and an asynchronous topology reducing the necessity for an additional external mosfet driver. all boost outputs use an external p-channel sequencing mosfet to isolate load from the battery when not needed. a low dropout (ldo) linear regulator with an adjustable 1.5v to 3.75v output provides a small dropout voltage and ripple free supply that is optimal for ?always on? microcontrollers. the ldo has a separate input supply pin. the SMB119 provides margining control over all of its output voltages. through an i 2 c command, all outputs can be margined by up to 10% of the nominal output voltage. the SMB119 also offers the ability to dynamically change output voltage level (7 steps) for two of its channels. in addition, each output is slew rate limited by soft-start circuitry that is user programmable and requires no external capacitors. all programmable settings on the SMB119 are stored in non-volatile registers and are easily accessed and modified over an industry standard i 2 c serial bus. for fastest possible production times summit offers an evaluation card and a graphical user interface (gui). general description
SMB119 summit microelectronics, inc 3 typical application SMB119 comp7 sw7 fb7 comp6 sw6 fb6 dgnd vdd nreset sda scl +0.5v to vin7(+2.5v typ) @ 500ma vbatt to +35v (+15v typ) @ 200ma +2.7 to +6.0v vdd_cap pwr_en compa4 +0.5v to +35v (+5v typ) @ 600ma buck or boost pchseq4 drvl4 drvh4 comp1 fb1 ldoout3 powerfail ldoin3 vin7 vin6 comp5 fb5 sw5 vin5 +1.5v to 3.75 @ 50ma compb4 alert# drvl7 drvl6 +0.5vto vin7(+2.5v typ) @ 500ma +0.5v to vin7(+2.5v typ) @ 500ma drvl5 drvl1 rsense1 csh1 csl1 vbatt to +35v (+15v typ) @ 200ma comp2 drvl2 fb2 rsense2 csh2 csl2 shdn vddp pchseq1 pchseq2 vin4 sys_en healthy figure 2 ? typical application schematic of the SMB119 (qfn-48) showing external circuitry necessary to configure the output channels as: step-up, ldo, and step-down.
SMB119 summit microelectronics, inc 4 pin descriptions pin number pin name pin type pin description 1 dgnd ground digital ground. connect to isolated pcb ground 2 pwr_en input enable input. pwr_en is programmable to activate one or more channels. this pin can be programmed to latch and act as a debounced, manual push button input. active high when level triggered, active low when used as a push- button input. 3 drvl4 output buck or boost converter low-side drive. connect to nfet gate 4 drvh4 output buck converter high-side drive. connect to pfet gate (for buck only) 5 vin4 power channel 4 controller power. connect to +2.7v to +6.0v to supply internal fet drivers 6 compa4 input channel 4 buck or boost outputs error amplifier input. connect this node to the type three r/c compensation network 7 pchseq4 output boost converter sequence. connect to pfet gate for boost channel on/off and sequencing. must be tied to ground when unused. 8 compb4 input channel 4 buck or boost outputs error amplifier output. connect this node to the type three r/c compensation network. 9 healthy output output monitor. open drain ac tive-high output asserts when all output channels are within uv/ov limits (ignoring disabled outputs) 10 power_fail output battery/input monitor. detects low input voltage. latched open-drain active high output. associated threshold must be set higher than nbatt_fault threshold. 11 comp6 input buck converter 6 compensation pin. connect to type 2 r/c compensation network 12 fb6 input buck converter 6 feedback pin. connect directly to output 13 sw6 input/output buck converter 6 switch pin. connect to drains of nfet 14 vin6 power buck converter 6 power. connect to +2.7v to +6.0v to supply internal pfet 15 drvl6 output buck converter 6 low-side drive. connect to nfet gate 16 sys_en input enable input. the sys_en pin is an active high programmable input used to enable (disable) selected supplies. when unused this pin should be tied to a solid logic level. 17 drvl7 output buck converter 7 low-side drive. connect to nfet gate 18 vin7 power buck converter 7 power. connect to +2.7v to +6.0v to supply internal pfet 19 sw7 input/output buck converter 7 switch pin. connect to drains of nfet 20 fb7 input buck converter 7 feedback pin. connect directly to output 21 comp7 input buck converter 7 compensation pin. connect to type 2 r/c compensation network 22 nreset output reset output. releases with programmable delay after all outputs are valid. open-drain active low output 23 pchseq1 output boost converter 1 sequence. connect to pfet gate for boost channel on/off and sequencing. must be tied to ground when unused. 24 vdd_cap power vdd bypass. connect to vdd bypass capacitor with 10uf capacitor. 25 vddp power power input for the boost and buck -boost converters. connect to +2.7v to +6.0v voltage source
SMB119 summit microelectronics, inc 5 pin descriptions (continued) pin number pin name pin type pin description 26 vbatt power power input for controller. connect to +2.7v to +6.0v voltage source 27 comp1 input boost converter 1 compensation pin. connect to r/c compensation network 28 csh1 input boost converter 1 current sense high . connect to high side of sense resistor 29 csl1 input boost converter 1 current sense low. connect to low side of sense resistor 30 fb1 input boost converter 1 feedback pin. connect to external resistor divider 31 drvl1 output boost converter 1 low- side drive. connect to nfet gate 32 drvl2 output boost converter 2 low- side drive. connect to nfet gate 33 fb2 input boost converter 2 feedback pin. connect to external resistor divider 34 csh2 input boost converter 2 current sense high . connect to high side of sense resistor 35 csl2 input boost converter 2 current sense low. connect to low side of sense resistor 36 comp2 input boost converter 2 compensation pin. connect to r/c compensation network 37 pchseq2 output boost converter 2 sequence. connect to pfet gate for boost channel on/off and sequencing. must be tied to ground when unused. 38 ldoin3 power ldo power input. connect to +2.7v to +6.0v to s upply internal ldo 39 ldoout3 input/output ldo output/feedback 40 sw5 input/output buck converter 5 switch pin. connect to drains of nfet 41 vin5 power buck converter 5 power. connect to +2.7v to +6.0v to supply internal pfet 42 drvl5 output buck converter 5 low-side drive. connect to nfet gate 43 fb5 input buck converter 5 feedback pin. connect directly to output 44 comp5 input buck converter 5 compensation pin. connect to type 2 r/c compensation network 45 shdn input shutdown. active high, disables all functions of the SMB119 for low power operation. shdn is by passed when dock_dc is present. 46 sda input/output i 2 c data 47 scl input i 2 c clock 48 nalert output fault interrupt. latched, open drain active low output. flag for all fault conditions (multiplexed) pad drvgnd ground power ground. internally connect to under package pad. connect to isolated pcb ground plane/flood
SMB119 summit microelectronics, inc 6 package and pin description SMB119 48-pad qfn top view 1 SMB119 7mm x 7mm qfn-48 (top view) 2 3 20 4 17 19 18 5 6 7 38 21 37 36 39 41 42 40 8 9 10 11 12 13 14 34 35 33 27 24 26 25 22 23 28 15 16 31 32 29 30 45 44 43 46 47 48 vin7 sw7 fb7 comp7 sda scl pchseq4 compa4 comp6 pwrfail vddp drvl6 vin6 sysen sw6 fb6 vin5 sw5 drvl5 fb5 comp5 csh2 drvl2 fb2 comp2 csl2 pchseq2 csh1 drvl1 fb1 comp1 csl1 pchseq1 pwren drvh4 drvl4 vin4 nalert nreset shdn dgnd compb4 vbatt ldoin3 ldoout3 drvl7 vddcap healthy figure 3 ? SMB119 7x7 qfn-48 pinout.
SMB119 summit microelectronics, inc 7 absolute maximum ratings recommended operating conditions temperature un der bias ...................... -55 c to 125 c storage temper ature............................ -65 c to 150 c terminal voltage with respect to gnd: vbatt............................................. -0.3v to +6.5v vin[7:5], ldoin3............................ -0.3v to +6.5v all others ........................................ -0.3v to +6.5v output short circ uit current ............................... 100ma lead solder temper ature ( 10 s).......................... 300 c junction temperature........ ...............?? .....?...150c esd rating per jedec???????....??..2000v latch-up testing per jedec???..?....?? 100ma commercial temperature range ................0c to +70c industrial temperature range ................ -40c to +85c vbatt.......................................................+2.7v to +6.0v vin[7:5], ldoin3 ......................................+2.7v to +6.0v package thermal resistance ( ja ) die paddle not attac hed to pcb .......................... 53 c/w die paddle attached to pcb............................. 22.9c/w moisture classification level 3 (msl 3) per j-std- 020 reliability characteristics data retentio n ................................................. 100 years endurance ................................................ 100,000 cycles dc operating characteristics (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) symbol parameter notes min typ max unit general v batt input supply voltage +2.7 +6.0 v vin[7:5], ldoin3 regulator power supply voltage +2.7 +6.0 v v batt rising 2.3 2.4 v v uvlo under-voltage lockout voltage v batt falling 2.1 v i dd-active active supply current all regulators and monitors enabled ? no load, v batt = 4.2v 3.3 4.5 ma i dd-standby standby supply current all regulators disabled, monitors active, v batt = 4.2v 130 300 a i dd-shutdown shutdown supply current all regulators and monitors disabled, note 4 0.6 5 a t shdn thermal shutdown temp 160 o c t hyst thermal shutdown temp hysteresis 20 o c vdd_cap voltage on vdd_cap pin all logic derived from this voltage, no load 2.4 2.5 2.6 v t = 0c to +70c 900 1000 1100 f osc oscillator frequency (note 1) t = -40c to +85c 850 1000 1150 khz note - the device is not guaranteed to function outside its operating rating. stresses listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions out side those listed in the operational sectio ns of the specification is not implied. exposure to any absolute maximum rating for extended period s may affect device performance and reliability. devices are esd sensitive. handlin g p recautions are recommended.
SMB119 summit microelectronics, inc 8 dc operating characteristics (continued) (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) symbol parameter notes min typ max unit channel [2:1] ? step-up boost v out voltage (nominal set point) v batt = 4.2v, i load = 0a vin +35 v v fb feedback voltage reference programmable in 4mv steps 0 1 v ? v fb feedback voltage accuracy at fb[2:1] pin (note 2) v fb =0.836v -3 1 +3 % g m error amp transconductance 145 umho i ea error amp output drive 20 a 0.8 r cs cs amplifier transresistance r sense = 0.1 ?, i load = 350ma 1.6 ? i ol-seq pchseq pull down current v ol-seq = 1v 60 100 a output high 6.0 ? r drvl ls gate drive impedance output low 2.5 ? v cl clamp threshold voltage programmable 1.0 1.5 v v cl_acc clamp threshold voltage accuracy clamp threshold 1.0 and 1.5v 5 % maximum (clamp on) 85 90 98 % d.c. duty cycle minimum, pwm mode 16 30 % channel 3 - ldo v out voltage (nominal set point) ldoin3=4.2v, i load =0a +1.5 +3.75 v ? v out voltage accuracy ldoin3=4.2v, i load =0a, v out =2.5v -2.5 0.5 +2.5 % ? v line line regulation ldoin3=4.2v, i load =0a, 1 mv/v ? v load load regulation vo=2.5, vin = 4.2v 1 mv/ ma ? v trans load transient regulation step load: 5ma to 50ma c out = 10uf 50 mv psrr input ripple rejection ldoin2=3.8v, v out =3.3v i load =50ma, v p-p =200mv, f=1khz 45 db i outmax maximum output current ldoin3=3.2v, v out =2.5v 50 75 ma v do dropout voltage i load =50ma 150 mv
SMB119 summit microelectronics, inc 9 dc operating characteristics (continued) (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) channel [7:5] ? step-down buck v out voltage (nominal set point) vin[7:5]=4.2v, i load =0a +0.5 vin v note 2, v out = 2.5v, t = -40c to +85c -2 1 +2 % ? v out voltage accuracy note 2, v out = 1.2v, t = 0c to +70c -2 1 +2 % v fb feedback voltage reference range programmable in 4mv steps 0 1 v g m error amp transconductance 160 umho i ea error amp output drive 20 a r cs cs amplifier transresistance i load = 500ma 1.2 ? r hs hs switch resistance i load = 500ma 320 m ? output high 5.5 ? r drvl ls gate drive impedance output low 2.7 ? v cl clamp threshold voltage programmable 1.0, 1.1, 1.2, 1.5v 1.0 1.5 v v cl_acc clamp threshold voltage accuracy clamp threshold 1.0 and 1.5v 5 % maximum, v batt = 4.2v 100 % d.c. duty cycle minimum, pwm mode, v batt = 4.2v 15 30 %
SMB119 summit microelectronics, inc 10 dc operating characteristics (continued) (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) channel 4 ? step-down buck or step-up boost v out voltage (nominal set point, buck) v batt =4.2v, i load =0a +0.5 +vin v v out voltage (nominal set point, boost) v batt =4.2v, i load =0a +vin +35 v v fb feedback voltage reference range programmable in 4mv steps 0 1 v ? v fb feedback voltage reference fb[4] pin, v fb = 0.660v, note 2 -2 +2 % a vol error amp open loop gain 60 db i ea error amp output drive 20 a i eab error amp input bias current 9 10 na output high 15 ? r drvh hs gate drive impedance (buck only) output low 15 ? output high 15 ? r drvl ls gate drive impedance output low 15 ? maximum, v batt = 4.2v 85 93 98 % d.c. (boost) duty cycle minimum, pwm mode, v batt = 4.2v 11 16 % maximum, v batt = 4.2v 100 % d.c. (buck) duty cycle minimum, pwm mode, v batt = 4.2v 7 11 %
SMB119 summit microelectronics, inc 11 note 1: contact summit factory for other frequency settings. note 2: voltage, current and frequency accuracies are only guaranteed for factory-programmed settings. changing any of these pa rameters from the values reflected in the customer s pecific csir code will result in ina ccuracies exceeding t hose specified above. note 3: the SMB119 device is not intended to function as a battery pack protector. battery packs used in conjunction with this device need to provide adequate internal protection and to comply with the corresponding battery pack specifications. note 4: guaranteed by design and characterization ? not 100% tested in production. dc operating characteristics (continued) (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) monitoring thresholds and logic inputs v ih input high voltage 0.7 x vdd_cap v v il input low voltage 0.3 x vdd_cap v v fb feedback voltage reference range programmable in 4mv steps 0 1 v v pbfth programmable nbatt_fault threshold range programmable in 150 mv increments 2.55 3.60 v ? v pbfth nbatt_fault accuracy v pbfth =3.15v -3 +4 % v ppfth programmable power_fail threshold range programmable in 150 mv increments 2.55 3.60 v ? v ppfth power_fail accuracy v ppfth =3.3v -3 +4 % -5 -10 -15 p uvth programmable under voltage threshold relative to nominal operating voltage. ch1 to ch7. note 3. -15 -20 -25 % 5 10 15 p ovth programmable over voltage threshold relative to nominal operating voltage. ch1 to ch7. note 4. 15 20 25 %
SMB119 summit microelectronics, inc 12 ac operating characteristics (continued) (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) symbol parameter notes min typ max unit 1.5 12.5 25 t ppto programmable power-on sequence timeout period. programmable power-on sequence position to sequence position delay. 50 ms 1.5 12.5 25 t dpoff programmable power-off sequence timeout period. programmable power-off sequence position to sequence position delay. 50 ms 25 50 100 t prto programmable reset time-out delay programmable time following assertion of last supply before nreset pin is released high. 200 ms off 50 100 t pst programmable sequence termination period time between active enable in which corresponding outputs must exceed there programmed under voltage threshold. if exceeded, a force shutdown will be initiated. 200 ms 0 25 100 t pdb pwr_en de-bounce period when pwr_en is programmed as power on pin. 400 ms t pfto power_fail timeout period timeout begins after latch is cleared. 3 ms t bfto nbatt_fault timeout period timeout begins after fault conditions cleared. 3 ms t pgf programmable glitch filter period for which fault must persist before fault triggered actions are taken. present on all buck, boost, and inverting supplies. 3 s
SMB119 summit microelectronics, inc 13 ac operating characteristics (continued) (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) symbol parameter notes min typ max unit 400 200 100 66.7 50 33.3 25 sr ref programmable slew rate reference adjustable slew rate factor proportional to output slew rate. 20 v/s
SMB119 summit microelectronics, inc 14 i 2 c-2 wire serial interface ac ope rating characteristics ?100 khz (over commercial operating conditions, unless otherw ise noted. all voltages are relative to gnd.) 100khz symbol description conditions min typ max units f scl scl clock frequency 0 100 khz t low clock low period 4.7 s t high clock high period 4.0 s t buf bus free time before new transmission - note 5 4.7 s t su:sta start condition setup time 4.7 s t hd:sta start condition hold time 4.0 s t su:sto stop condition setup time 4.7 s t aa clock edge to data valid scl low to valid sda (cycle n) 0.2 3.5 s t dh data output hold time scl low (cycle n+1) to sda change 0.2 s t r scl and sda rise time note 5 1000 ns t f scl and sda fall time note 5 300 ns t su:dat data in setup time 250 ns t hd:dat data in hold time 0 ns ti noise filter scl and sda noise suppression 100 ns t wr_config write cycle time config configuration registers 10 ms t wr_ee write cycle time ee memory array 5 ms note 5: guaranteed by design figure 4: i 2 c timing diagram timing diagrams t r t f t high t low t su:sta t hd:sta t su:dat t hd:dat t su:sto t buf t dh t aa scl sda (in) sda (out) t wr (for write operation only) i 2 c timing diagrams
SMB119 summit microelectronics, inc 15 channel 4 buck 3.3v buck 1.2v boost 5v buck 2.5v boost 12v buck 1.8v buck 3.3v channel 4 boost 15v 60 65 70 75 80 85 90 95 100 0 0.2 0.4 0.6 0.8 current (amps) efficiency (%) 5.0v 4.2v 3.8v 3.6v 60 65 70 75 80 85 90 95 100 0 0.2 0.4 0.6 0.8 current (amps) efficiency (%) 5.0v 4.2v 3.8v 3.6v 3.3v 3.0v 60 65 70 75 80 85 90 95 100 0 0.2 0.4 0.6 0.8 current (amps) efficiency (%) 5.0v 4.2v 3.8v 3.6v 3.3v 3.0v 60 65 70 75 80 85 90 95 100 0 0.2 0.4 0.6 0.8 current (amps) efficiency (%) 5.0v 4.2v 3.8v 3.3v 3.0v 60 65 70 75 80 85 90 95 100 0 0.2 0.4 0.6 0.8 current (amps) efficiency (%) 4.8v 4.2v 3.8v 3.6v 3.3v 3.0v 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 current (amps) efficiency (%) 5.0v 4.2v 3.8v 3.6v 3.3v 3.0v 60 65 70 75 80 85 90 95 100 0 0.05 0.1 0.15 current (amps) efficiency (%) 5.0v 4.2v 3.8v 3.6v 3.3v 3.0v 60 65 70 75 80 85 90 95 100 00.511.522.5 current (amps) efficiency (%) 5.0v 4.2v 3.8v 3.6v 3.4v efficiency graphs buck 1.8v buck 3.3v
SMB119 summit microelectronics, inc 16 figure 6: light load inductor current in asynchronous mode. time/horizontal division = 10 s ch 4 (50ma/div) = 1.5v (ch 7) converter output (green trace) figure 5: light load inductor current in constant frequency mode (pwm). time/horizontal division = 1 s ch 4 (50ma/div) = 1.5v (ch 7) converter output (green trace) voltage and current waveforms
SMB119 summit microelectronics, inc 17 figure 7: pulse skipping on lsdrv pin while in pfm mode of operation. switching frequency is proportional to load. time/horizontal division = 1ms ch 1(2v/div) = lsdrv output (yellow trace) ch 4 (50ma/div) = 150ma load step (green trace) figure 8: pulse skipping on lsdrv pin while in pfm mode of operation. switching frequency is proportional to load. time/horizontal division = 200 s ch 1(2v/div) = lsdrv output (yellow trace) ch 4 (50ma/div) = 150ma load step (green trace) figure 9: pulse skipping on lsdrv for light load pfm operation time/horizontal division = 4 s ch 1(2v/div) = lsdrv output (yellow trace) figure 10: forced pwm operation. time/horizontal division = 4 s ch 1(2v/div) = lsdrv output (yellow trace) voltage and current waveforms (continued)
SMB119 summit microelectronics, inc 18 applications information device operation power supply the SMB119 can be powered from an input voltage between +2.7 and +6.0 volts applied between the vbatt pin and ground. the SMB119 is optimized for use with a rechargeable single cell lithium ion battery, but may also be powered from a rectified ac adaptor or three aa batteries. the input voltage applied to the vbatt pin is filtered by an external filter capacitor attached between the vdd_cap pin and ground; this filtered voltage is then used as an internal vdd supply. the vdd_cap node is monitored by an under-voltage lockout (uvlo) circuit, whic h prevents the device from turning on when the voltage at this node is less than the uvlo threshold. shutdown a shutdown pin is provid ed, that disconnects power from the SMB119 and reduces the current consumption to 0.1 a when asserted. in this mode all channels are shut off. when asserted the SMB119 will not respond to i 2 c commands. once the voltage on the vbatt input supply pin exceeds the uvlo threshold a 10 to 20ms delay must pass before supplies can be enabled. during this period the non-volatile registers are initialized with the default values from the nonvolatile memory. power-on/off control sequencing can be initiated: automatically, by a volatile i 2 c power on command, or by asserting the pwren pin. when the pwren pin is programmed to initiate sequencing, it can be level or edge triggered. the pwren input has a programmable de-bounce time of 100, 50, or 25ms. the de-bounce time can also be disabled. when configured as a push-button enable, pwren must be asserted longer than the de-bounce time before sequencing can commence, and pulled low for the same period to disable the channels. independent channel enable control each output can be enabled and disable by an enable signal. the enable signal is can be provided from either the enable pins or by the contents of the enable register. when enabling a channel from the enable register, the register contents default stat e must be set so that the output will be enabled or disabled following a por (power on reset). when default on is selected, the c hannel will turn on after its sequence position is reached or power is applied?depending on the sequencing type. when default off is selected, the channel will not turn on until sequencing each channel on the SMB119 may be placed in any one of 7 unique sequence positions, as assigned by the configurable non-volatile register contents. the SMB119 navigates between each sequence position using a feedback-based cascade-sequencing circuit. cascade sequencing is the process in which each channel is continually compared against a programmable reference voltage until the voltage on the monitored channel exceeds the reference voltage, at which point an internal sequence position counter is incremented and the next sequence position is entered. in the event that a channels enable input is not asserted when the channel is to be sequenced on, that sequence position will be skipped and the channel in the next sequence posi tion will be enabled. figure 11 ? power on sequencing waveforms. time = 4ms/devision, scale = 1v/devision ch 1 = 3.3v output (yellow trace) ch 2 = 2.5v output (blue trace) ch 3 = 1.8v output (purple trace) ch 4 = 1.2v output (green trace)
SMB119 summit microelectronics, inc 19 applications information (continued) power on/off delay there is a programmable delay between when channels in subsequent sequence positions are enabled. the delay is programmable at 50, 25, 12.5 and 1.5ms intervals. this delay is programmable for each of the seven sequence positions. manual mode the SMB119 provides a manual power-on mode in which each channel may be enabled individually irrespective of the state of other channels. in this mode, the enable signal has complete control over the channel, and all sequencing is ignored. in manual mode, channels will not be disabled in the event of a uv/ov fault on any output or the vbatt pin. force-shutdown when a battery fault occurs, a uv/ov is detected on any output, or an i 2 c force-shutdown command is issued, all channels will be immediately disabled, ignoring sequence positions or power off delay times. sequence termination timer at the beginning of each s equence position, an internal programmable timer will begin to time out. when this timer has expired, the SMB119 will automatically perform a force-shutdown operation. this timer is user programmable with a programmable sequence termination period (t pst ) of 50, 100, 200 ms; this function can also be disabled. power off sequencing the SMB119 has a power-off sequencing operation. during a power off operation, the supplies will be powered off in the reverse order they where powered on in. when a power-off command is issued the SMB119 will set the sequence position counter to the last sequence position and disable that channel without soft-start control; once off, the power off delay for the channel(s) in the next to last sequenc e position will begin to timeout, after which that channel(s) will be disabled. this process will continue until all channels have been disabled and are off. the programmable if a channel fails to turn off within the sequence termination period, the sequence termination timer will initiate a force shutdown, if enabled. input and output monitoring the SMB119 monitors all outputs for under-voltage (uv) and over-voltage (ov) faults. the monitored levels are user programmable, and may be set at 5, 10, 15, and 20 percent of the nominal output voltage. the vbatt pin is monitored for two user- programmable uv settings. the vbatt uv settings are programmable from 2.55v to 3.45v in 150mv increments. once the uv/ov voltage set points have been violated, the SMB119 can be programmed to respond in one of three wa ys, perform: a power-off operation, a force-shutdown operation and-or it can trigger the nreset/healthy pin. soft start the SMB119 provides a programmable soft-start function for all pwm outputs. the soft-start control limits the slew rate that each output is allowed to ramp up without the need for an external capacitor. the soft start slew rate is proportional to the product of the output voltage and a slew rate reference. this global reference is programmable and may be set to 400, 200, 100, 67, 50, 33, 25, and 20 volts per second. the slew rate control can also be disabled on any channel not requiring the feature. + ? vref r1 r2 comp1 vout vout= vref* (1 + r2/r1) soft-start slew rate=srref* (1 + r2/r1) figure 12 ? the output voltage is set by the voltage divider . the vref voltage is programmable from 0 to 1.0 volt in 4mv increments via the i 2 c interface
SMB119 summit microelectronics, inc 20 figure 13 ? power-on sequencing flow chart. applications information (continued) restart after pow er- off or force-shutdow n i 2 c power on command begin sequencing sequence position 1 normal sequencing current sequence position sequencing w ith enable sequencing w ith channel bypass channel-specific programmable options enable = pw ren pin or i 2 c pw r enable bit pow er on delay pow er on delay pow er on delay next sequence position wait for enable enable lo w enable high enable high enable lo w soft- start w a it f o r enable vout<=uv monitor vout<=uv soft- start enable high enable lo w pw ren pin asserted enable = pw ren pin or i 2 c pw r enable bit
SMB119 summit microelectronics, inc 21 applications information (continued) battery monitoring the battery voltage is monitored for two user- programmable uv settings via the vbatt pin. monitoring is accomplish ed by a comparator-based approach, in which a programmable voltage reference is compared against the monitored signal. each channel possesses a dedicated reference voltage generated by a programmable level shifting digital to analog converter. the SMB119 contains two user programmable voltage- monitoring levels (power_fail, nbatt_fault), one of which triggers a corresponding status pin when exceeded. battery voltage, like all monitored voltages, is compared against a user programmable voltage set internally by a digital to analog converter. when asserted, the power_fail pin is latched and will not be released as long as the voltage on the battery is below the power_fail level. once the voltage on the battery has risen above the power_fail level the following condition will clear the latch and allow the power_fail pin to be released: an i 2 c power fail clear command is issued. once this condition has been met, the power_fail pin will be released after a power-fail timeout period (t pfto ) of 3.0-4.5ms. the power_fail level is user programmable from 2.55-3.6.0v at 150 mv increments. when the voltage at the vbatt pin falls below the second user programmable level, the active low nbatt_fault pin will be asserted. this pin is not latched and is used to indicate the impending loss of power to the SMB119. after the nbatt_fault pin has been asserted, a battery fault timeout period (t bfto ) of 3.0-4.5ms must pass in which the battery voltage exceeds the nbatt_fault th reshold before it will be released. the nbatt_fault threshold is user programmable from 2.55-3.6.0v at 150 mv increments. upon assertion of either the nbatt_fault or power_fail pin the SMB119 can be programmed to respond in one of three ways, it may perform: a power- off operation, a force-shutdown operation, or take no action. when programmed to perform a power-off or force-shutdown operation the SMB119 can optionally be programmed to latch the outputs off until the power on pin is toggled or an i 2 c power-on command is issued. ldo standby voltage the ldo has a programmable output voltage from 1.5v to 3.75v. it is capable of supplying up to 80ma and has uv and ov monitoring levels with corresponding fault responses. the channel 3 ldo can be sequenced on in any of the eight sequence positions, and can be enabled and disabled at any time. soft start the SMB119 provides a programmable soft-start function for all pwm outputs. the soft-start control limits the slew rate that each output is allowed to ramp up without the need for an external capacitor. the soft start slew rate is proportional to the product of the output voltage and a slew rate reference; see figure 6. this global reference is programmable and may be set to 400, 200, 100, 67, 50, 33, 25, and 20 volts per second. the slew rate control can also be disabled on any channel not requiring the feature. output voltage the pwm output voltages are set by a resistive voltage divider from the output to the comp1 node. for the buck channels (ch[7:5]), the vo ltage divider is internal to the part and programmable. the resistive divider may be set by adjusting a 100k ? resistor string with 8 taps from r1 = 20-90k ? . for the boost outputs (ch[2:1]), the resistive di vider is external and any appropriate value of r1 an r2 can be chosen. the reference voltage that sets the output is user programmable, and may be set anywhere from 0-1.000 volt at 4mv increments. programmable switching frequency the SMB119 has a 1000khz switching frequency. if a different frequency is desirable, please contact the summit factory. dynamic voltage management the SMB119 has three voltage settings, nominal, margin high, and margin low. the nominal setting is the voltage that the converter regulates at by default, while the margin high and margin low voltages are transitioned to by means of a volatile i 2 c write command. a status register is provided to indicate the current margin state of each channel. a seven level margining option is also available for channels 4 and 5 of the SMB119 device. when enabled, seven level margining allows channels 4 and 5 to be dynamically modified to one of seven pre- determined voltage levels. when seven level margining is enabled channels 3, 6 and 7 loose the margin high and margin low settings. while a channel is dynamically changing its voltage the uv/ov flags can be disabled temporarily, allowing the channels time to reached the new voltage settings. note: configuration writes or reads of registers should not be performed while dynamic voltage management.
SMB119 summit microelectronics, inc 22 buck converters the SMB119 has three synchronous buck converters with integrated p-channel mosfets and a driver for an external nfet, see figure 14. each channel has an output voltage range from the input supply to approximately 0.5v. buck channel asynchronous operation the buck converters use either a constant frequency or variable frequency current mode control technique. during the fixed frequency pwm mode of operation, the converter switches at a fixed frequency and modulates the duty cycle to attain the correct output voltage. this can lead to ?charge shuttling? under light load conditions were the charge transferred to the output capacitor during the on time of the pfet is discharged to ground during the on time of the nfet. this mode of operation is desirable in sit uations requiring low voltage ripple, the ability to sink cu rrent, or a known switching frequency for all loads. during the pfm mode of operation the converter operates asynchronously where the nfet is held off and the body diode of the fet is used as a ?catch? diode; preventing the voltage on the switch node from falling below ground by more than a diode drop. it is desirable to operate asynchronously under light load so that charge shuttling does not occur. the asynchronous operation allows the converter to only switch when the voltage falls below the error amplifier reference voltage. while it is advantageous to operate asynchronously for light load currents, it is less efficient for moderate loads where the power loss across the forward voltage drop of the diode leads to decreased efficiency. to increase the efficiency for these moderate load conditions an external schottky diode can be placed in parallel with the body diode of the fet. to maximize the converter efficiency for both light and heavy loads the buck converters automatically switch from pfm to pwm mode. t he pwm to pfm crossover is accomplished by observing the voltage on the comp pin, the voltage on the comp pin is directly proportional to the load current. when the voltage on the comp pin falls below a programmable reference, the converter operates in pfm. the nfet driver will stay in the off state until the voltage on the comp pin rises above the pfm to pwm crossover voltage. each channel has an over current protection mechanism. when a channel reaches its current limit, the output voltage will be reduced as the load rises. this is accomplished by clamping the comp node to one of four programmable se ttings. the over-current level can be programmed to four different levels by clamping the error amplifier's output voltage to a programmable voltage. all current limits and pfm to pwm crossover currents are calculated by the gui interface. the output of all buck converters is determined by the portion of the switching period for which the inductor voltage is at the converter supply voltage; this percentage is referred to as the duty cycle. for a buck channel operating synchronously, duty cycle and the output voltage are related by equation 1 below: equation 1: vin d vo * = each buck converter can operate up to 100% duty cycle allowing the output to equal the input. the minimum voltage is determined by the minimum duty cycle listed in the electrical specifications section. for a buck converter operating in pfm mode the duty cycle is essentially 0% implying that the output can go to ground. each converter has a separate vin input used to power the converter. this supply attaches to the source of the integrated pfet. it is important to connect an input (or bulk) as close to the vin pin as possible. for information on the type of capacitor to use, refer to the component selection section. applications information (continued) sw vin drvl pwm comp vo comp fb figure 14 ? buck channel with internal pfet.
SMB119 summit microelectronics, inc 23 boost controllers the SMB119 has two asynchronous current mode boost converters with over-c urrent protection and either a pwm or pfm mode of operation. when configured as a current mode boost, a sense resistor must be added, externally, in series with the source of the n-channel mosfet, see figure 15. the over-current circuitry is identical to that descried for the buck converter, and the current limit is displayed in the gui. the pwm to pfm crossover current is identical to the circuitry used for the buck converter, we monitor the voltage on the comp node and when the voltage is below a programmable reference the nfet is held off. the boost converter has a fixed pwm option, when enabled the boost channel will switch every cycle keeping the ripple voltage low. care must be taken in selecting the pwm option on the boost channel, as this converter does not have the ab ility to shuttle charge. as a result, the load must be sufficient to deplete the deposited charge every cycle or else the output voltage will rise above the output set point. the driver supplies for the boost converters are powered from the vddp supply pin. therefore, without voltage on the vddp input the boost converters will not function. the output of all boost channels is determined by the portion of the switching period for which the inductor voltage is at ground; this percentage is referred to as the duty cycle. for a b oost converter, when the inductor current does not go to zero amperes during the cycle (ccm), the relation between the duty cycle and the output voltage is determined by equation 2: equation 2: vin d vo * 1 1 ? ? ? ? ? ? ? = the maximum duty cycle the boost converter can achieve is determined by the max duty cycle spec in the electrical specificati on section of the datasheet. boost or buck controller the SMB119 has one voltage mode output that can be configured as either a boost or a buck converter, but not both; see figures 16 and 17. when configured as a buck the output voltage can only be less than or equal to the input voltage. when a hardware modification is preformed, the output can function as a boost, whose output voltage is greater than the input voltage. as a voltage mode converter, this channel has no inherent over current protection and requires a type three- compensation network. since the fets are external for this channel, the output current capabilities can be scaled by choosing larger components. figure 15: boost converter figure 16: buck or boost configures as boost figure 17: buck or boost configures as buck pchseq vin drvl pwm compensation comp fb boost vout vddp sequencing csh csl rcs applications information (continued) pchseq vin drvl pwm comp compa buck vout vin sequencing compb drvh pchseq vin drvl pwm comp compa boost vout vin sequencing compb x drvh
SMB119 summit microelectronics, inc 24 component selection inductor: the starting point design of any and dc/dc converter is the selection of the appropriate inductor for the application. the optimal inductor value will set the inductor current at 30% of the maximum expected load current. the inductors current for buck and boost converters are as follows: buck: equation 3: f i vin vo v vo l max in * * 3 . 0 * ) ( ? = boost: equation 4: f i v v v v l max o in o in * * 3 . 0 * ) ( ? = where vo is the output voltage, vin is the input voltage, f is the frequency, and i max is the max load current. for example: for a 1.2v output and a 3.6v input with a 500ma max load, and a 1mhz switching frequency the optimal inductor value is: uh e l 3 . 5 6 1 * 5 . 0 * 3 . 0 * 6 . 3 ) 2 . 1 6 . 3 ( 2 . 1 = ? = choosing the nearest standard inductor value we select a 5.6uh inductor. it is import ant that the inductor has a saturation current level greater than 1.2 times the max load current. other parameters of interest when selecting an inductor are the dcr (dc winding resist ance). this has a direct impact on the efficiency of the converter. in general, the smaller the size of the inductor is the larger the resistance. as the dcr goes up the power loss increases according to the i 2 r relation. as a result choosing a correct inductor is often a trade off between size and efficiency. input capacitor each converter should have a high value low impedance input (or bulk) capacitor to act as a current reservoir for the converter st age. this capacitor should be either a x5r or x7r mlcc (multi-layer-ceramic capacitor). the value of this capacitor is normally chosen to reflect the ratio of the input and output voltage with respect to the output capacitor. typical values range from 2.2uf to 10uf. for buck converters, the input capacitor supplies square wave current to the inductor and thus it is critical to place this capacitor as close to the pfet as possible in order to minimize trace inductance that would otherwise limit the rate of change of the current. while the placement of this inductor for boost channels is not as critical as with the buck channels, each boost must still have its own rese rvoir capacitor. output capacitor each converter should have a high value low impedance output capacitor to act as a current reservoir for current transients and to. this capacitor should be either a x5r or x7r mlcc. for a buck converter, the value of this capacitance is determined by the maximum expected transient current. since the converter has a finite response time, during a load transient the current is provided by the output capacitor. since the voltage across the capacitor drops proportionally to the capacitance, a higher output capacitor reduces the voltage drop until the feedback loop can react to increase the voltage to equilibrium. for the boost converters, the output is disconnected from the inductor while the diode is reverse biased. this means that the entire load current is being taken from the output capacitance for this portion of the duty cycle. for this reason it is necessary to choose the output capacitor such that the cycle-to-cycle voltage droop is minimized to be within system limits. the voltage drop can be calculated according to: equation 5 : where i is the load or transient current, t is the time the output capacitor is supporting the output and c is the output capacitance. typical values range from 10uf to 44uf. other important capacitor parameters include the equivalent series resistance (e.s.r) of the capacitor. the esr in conjunction with the ripple current determines the ripple voltage on the output, for typical values of mlcc the esr ranges from 2-10m ? . in addition, carful attention must be paid to the voltage rating of the capacitor the voltage rating of a capacitor must never be exceeded. in addition, the dc bias voltage rating can reduce the measured capacitance by as much as 50% when the voltage is at half of the max rating, make sure to look at the dc bias de-rating curves when selecting a capacitor. mosfets when selecting the appropriate fet to use attention must be paid to the gate to source rating, input capacitance, and maximum power dissipation. c t i v * = applications information (continued)
SMB119 summit microelectronics, inc 25 most fets are specified by an on resistance (rds on ) for a given gate to source voltage (v gs ). it is essential to ensure that the fets used will always have a v gs voltage grater then the minimum value shown on the datasheet. it is worth noting that the specified v gs voltage must not be confused wi th the threshold voltage of the fet. the input capacitance must be chosen such that the rise and fall times specified in the datasheet do not exceed ~5% of the switching period. to ensure the maximum load current will not exceed the power rating of the fet, the power dissipation of each fet must be determined. it is important to look at each fet individually and then add the power dissipation of complementary fets after the power dissipation over one cycle has been determined. the power dissipation can be approximated as follows: equation 6: on l dson t i r p * * ~ 2 where t on is the on time of the primary switch. t on can be calculated as follows: equations 7, 8, 9: t v v v boost t v v pfet buck t v v nfet buck o in o in o in o * ) ( : * : * ) 1 ( : ? ? ? ? compensation: summit provides a design tool to called summit power designer? that will automatically calculate the compensation values for a design or allow the system to be customized for a particular application. the power designer software can be found at http://www.summitmicro.com/prod_select/xls/summitpo werdesigner_install.zip . applications information (continued)
SMB119 summit microelectronics, inc 26 r42 100 c5 0.1uf led+ u1 SMB119 dgnd 1 pwren 2 drvl4 3 drvh4 4 vin4 5 compa4 6 pchseq4 7 compb4 8 power_fail 10 comp6 11 fb6 12 sw6 13 vin6 14 drvl6 15 sysen 16 vin7 18 sw7 19 fb7 20 comp7 21 nreset 22 pchseq1 23 vdd_cap 24 vddp 25 vbatt 26 comp1 27 csh1 28 csl1 29 fb1 30 drvl1 31 drvl2 32 fb2 33 csh2 34 csl2 35 comp2 36 pchseq2 37 ldoin3 38 ldoout3 39 sw5 40 vin5 41 drvl5 42 fb5 43 comp5 44 shdn 45 sda 46 scl 47 gnd 49 drvl7 17 nalert 48 healthy 9 r17 49.9k c1 0.1uf c2 1uf c9 0.1uf c10 10uf vbatt vin5 fb2 r4 47k c50 0.1uf r18 49.9k c51 10uf vbatt vin7 q5 si1406dh 3 1 4 2 5 6 l2 10uh r15 3 r31 3 c21 10uf vin4 c22 3900pf c23 np d9 schottky c36 4.7uf c37 0.1uf sw1 r25 100k c39 680pf q2(p) q1(n) q2 fdc6333 r26 rcs 0.1 q4 si1406dh 3 1 4 2 5 6 l5 10uh c40 10uf r29 100k c42 0.1uf nalert c11 0.1uf r19 49.9k c12 10uf q6 si1406dh 3 1 4 2 5 6 optional constant current led circuitry l3 10uh vin6 vin5 r16 3 d20 diode zener c25 10uf c26 3900pf c27 np vbatt vin6 vbatt fb2 nreset r49 90.9k r50 6.8k l1 10uh r44 3 do not populate with led load r39 rcs 0.1 vbatt d16 500ma c43 10uf c44 0.1uf r40 100k c46 680pf q2(p) q1(n) q11 fdc6420 l7 10uh power_fail c47 10uf r46 90.9k r47 6.8k r48 100k c49 0.1uf sda r3 47k r41 100 optional switches healthy ch3 vbatt vbatt c3 0.1uf c4 1uf scl ch1 r14 3 c13 0.1uf c14 1uf sysen sw2 sw slide-spdt 1 2 3 ch4 pwren vin7 ch7 r43 100 ch5 c19 10uf ch6 d11 d17 d18 d19 d12 led white led+ r66 20 d13 d14 d15 c15 0.1uf ch2 c16 3900pf c17 np vbatt r6 47k r67 1k r7 47k vbatt q2(p) q1(n) q1 fdc6420 r30 3 l4 10uh 2a vbatt c28 10uf c29 0.1uf c7 0.1uf c30 10uf c8 10uf r20 80.6k r22 499 vbatt c33 150pf vin4 r21 20k c34 22pf r23 20k c35 470pf applications information (continued) figure 18 ? applications schematic shown the SMB119 programmable power manager.
SMB119 summit microelectronics, inc 27 development hardware & software the end user can obtain the summit smx3200 programming system for device prototype development. the smx3200 system consists of a programming dongle, cable and windows tm gui software. it can be ordered on the website or fr om a local representative. the latest revisions of all software and an application brief describing the smx3200 is available from the website ( www.summitmicro.com ). the smx3200 programming dongle/cable interfaces directly between a pc?s parallel port and the target application. the device is t hen configured on-screen via an intuitive graphical user interface employing drop- down menus. the windows gui software will generate the data and send it in i 2 c serial bus format so that it can be directly downloaded to the SMB119 via the programming dongle and cable. an example of the connection interface is shown in figure 19. when design prototyping is complete, the software can generate a hex data file that should be transmitted to summit for approval. summit will then assign a unique customer id to the hex code and program production devices before the final electrical test operations. this will ensure proper devic e operation in the end application. pin 9, 5.0v pin 7, 10v pin 5, reserved pin 3, gnd pin 1, gnd pin 6, mr# pin 4, sda pin 2, scl pin 8, reserved pin 10, reserved top view of straight 0.1" x 0.1 closed-side connector. smx3200 interface cable connector. 9 7 5 3 1 10 8 6 4 2 SMB119 sda scl gnd 0.1 f figure 19 ? smx3200 programmer i 2 c serial bus connections to program the SMB119.
SMB119 summit microelectronics, inc 28 i 2 c programming information serial interface access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standar d 2-wire serial interface (i 2 c). sda is a bi-directional data line and scl is a clock input. data is clocked in on the rising edge of scl and clocked out on the falling edge of scl. all data transfers begin with the msb. during data transfers, sda must remain stable while scl is high. data is transferred in 8-bit packets with an intervening clock period in which an acknowledge is provided by the device receiving data. the scl high period (t high ) is used for generating star t and stop conditions that precede and end most transactions on the serial bus. a high-to-low transition of sda while scl is high is considered a start condition while a low-to-high transition of sda while scl is high is considered a stop condition. the interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. the address byte is comprised of a 7-bit device type identifier (slave address). the remaining bit indicates either a read or a write operation. refer to table 1 for a description of the address bytes used by the SMB119. the device type identifier for the memory array, the configuration registers an d the command and status registers are accessible with the same slave address. the slave address can be can be programmed to any seven bit number 0000000 bin through 1111111 bin . write writing to the memory or a configuration register is illustrated in figu res 20, 21, 23, and 24. a start condition followed by the slave address byte is provided by the host; the SMB119 or SMB119x respond with an acknowledge; the host then responds by sending the memory address pointer or configuration register ad dress pointer; the SMB119 responds with an acknowledge; the host then clocks in one byte of data. for memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. after the last byte is clocked in and the host receives an acknowledge, a stop condition must be issued to initiate the nonvolatile write operation. read the address pointer for the non-volatile configuration registers and memory registers as well as the volatile command and status registers must be set before data can be read from the SMB119. this is accomplished by issuing a dummy write command, which is a write command that is not followed by a stop condition. a dummy write command sets the address from which data is read. after the dummy write command is issued, a start command follo wed by the address byte is sent from the host. the host then waits for an acknowledge and then begins clocking data out of the slave device. the first byte read is data from the address pointer set during the dummy write command. additional bytes can be clocked out of consecutive addresses with the host providing an acknowledge after each byte. after the data is read from the desired registers, the read operation is terminated by the host holding sda high during the acknowledge clock cycle and then issuing a stop condition. refer to figures 22, and 25 for an illustration of the read sequence. configuration registers the configuration registers are grouped with the general-purpose memory. writing and reading the configuration registers is shown in figures 20, 21 and 22. general-purpose memory the 96-byte general-purpose memory block is segmented into two continuous independently lockable blocks. the first 48-byte memory block begins at register address pointer a0 hex and the second memory block begins at the r egister address pointer c0 hex ; see table 2. each memory block can be locked individually by writing to a dedicated register in the configuration memory spac e. memory writes and reads are shown in figures 23, 24, and 25.
SMB119 summit microelectronics, inc 29 graphical user interface (gui) device configuration ut ilizing the windows based SMB119 graphical user interface (gui) is highly recommended. the software is available from the summit website ( www.summitmicro.com ). using the gui in conjunction with this datasheet, simplifies the process of device prototyping and the interaction of the various functional blocks. a programming dongle (smx3200) is available from summit to communicate with the SMB119. the dongle connects directly to the parallel port of a pc and programs the device through a cable using the i 2 c bus protocol. see figure 19 and the smx3200 data sheet. slave address register type configuration registers are located in 00 hex thru 9f hex general-purpose memory block 0 is located in a0 hex thru bf hex any general-purpose memory block 1 is located in c0 hex thru ff hex table 2 - address bytes used by the SMB119. i 2 c programming information (continued)
SMB119 summit microelectronics, inc 30 s t a r t bus address w a c k master slave a c k configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 20 ? configuration register byte write s t a r t bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 21 ? configuration register page write i 2 c programming information (continued)
SMB119 summit microelectronics, inc 31 s t a r t bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k bus address a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 22 - configuration register read s t a r t bus address w a c k master slave a c k configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 23 ? general purpose memory byte write bus address s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 24 ? general purpose memory page write i 2 c programming information (continued)
SMB119 summit microelectronics, inc 32 s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) bus address bus address a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 25 ? general purpose memory read i 2 c programming information (continued)
SMB119 summit microelectronics, inc 33 package
SMB119 summit microelectronics, inc 34 summit SMB119n ayyww pin 1 annn summit part number date code (yyww) part number suffix (contains customer specific ordering requirements) lot tracking code (summit use) drawing not to scale xx status tracking code (01, 02, 03...) (summit use) product tracking code (summit use) l 100% sn, rohs compliant SMB119 n package n = 48-pad qfn summit part number specific requirements are contained in the suffix nnn part number suffix l l = 100% sn, rohs compliant c c = commercial temperature range environmental attribute blank = industrial notice note 1 - this is a final data sheet that describes a summit product currently in production. summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to impr ove design, performance or reliability. summit microelectronics, inc. assumes no responsib ility for the use of any circuits describ ed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect repres entative operating parameters, and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc . shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affe ct their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receive s written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all su ch risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. revision 3.0 - this document supersedes all previous versions . please check the summit microelectronics inc. web site at www.summitmicro.com for data sheet updates. ? copyright 2006 summit microelectronics, inc. programmable power for a green planet? i 2 c is a trademark of philips corporation xscale is a trademark of marvell technology group ltd. part marking ordering information

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